My last post, Applying Agile to Hardware Development, examined how Agile is currently being investigated and applied to developing and verifying hardware designs — not simply software or firmware. An obvious place where unit-testing and TDD should also be extrapolated is logic design. After all, logic is typically designed with a programming language. Hundreds of frameworks are available for unit-testing in nearly every language. But what about the world of logic design that is dominated by Verilog and its cousin VHDL? As it turns out, there are some tools bubbling up to the surface, and SVUnit is an interesting alternative to the Verilog crowd.
The folks over at Agile SoC have been taking on the challenge of applying Agile to logic design for some time now. Last month was officially TDD month at Agile SoC, where their group took some serious time investigating how to really make TDD happen in this realm. Logic design is primarily accomplished by either VHDL (VHSIC Hardware Description Language) or by Verilog. The guys at Agile SoC have decided to focus on tackling this problem from from the Verilog side; specifically, they have taken advantage of recent extensions to Verilog available in SystemVerilog. SystemVerilog provides much needed features to Verilog, but also introduces object-oriented techniques for the verification side that have brought Verilog into the new millennium.
Originally introduced at the SNUG (Synopsys Users Group) Conference in 2009, SVUnit (SystemVerilog Unit) is now gaining attention from Agile SoC. Over the past month, they have dedicated significant effort to determine if SVUnit is up to the challenge of making TDD realistic in the world of HDLs. Their endeavor has proven that it is a promising adventure. This will likely change the HDL world by making TDD realizable in the world of ASICs and FPGAs.
The SVUnit archtecture was inspired by the popular JUnit framework. This is not too surprising, since it seems that the OO extensions SystemVerilog provides were somewhat inspired by Java. This is made evident by looking at the architecture of a test suite in SVUnit:
As you can see, the same basic unit-testing terms are used. A group of
svunit_testcases comprise an
svunit_testsuite. Likewise, one or more
svunit_testsuites get corralled together to comprise an
teardown() are available as well. To keep things simple, there are two basic assertions available:
FAIL_UNLESS(). These can be used to create much more powerful assertions to verify the result of individual behaviors and facilitate test-first development.
The people at Agile SoC have also put together scripts that make the generation of test suites and runners trivial. Decreasing the overhead of TDD is very crucial to its success. Burning a full die of ASICs at a chip fab is MUCH more expensive and takes tons more design, setup, time, and, obviously, money. It seems that for SVUnit and TDD, this is a logical step for the ASIC community to take, since the cost of a bug is so expensive. FPGAs undoubtedly lessen the cost of change, since they are reprogrammable. Although it isn’t hard to imagine that logic design will be forever transformed as TDD takes a foothold, and the rest of Agile comes along for the ride.